Methods for fabrication of bonded wafers and surface acoustic wave devices using same

ABSTRACT

A method of fabricating a bonded wafer with low carrier lifetime in silicon comprises providing a silicon substrate having opposing top and bottom surfaces, modifying a top portion of the silicon substrate to reduce carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion, bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate, and providing a pair of electrodes having fingers that are inter-digitally dispersed on a top surface of the piezoelectric layer, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. The modifying and bonding steps may be performed in any order. The modified top portion of the silicon substrate prevents the creation of a parasitic conductance within that portion during operation of the SAW device.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/087,423, filed Mar. 31, 2016, which claims the benefit of provisionalpatent application Ser. No. 62/197,650, filed Jul. 28, 2015, thedisclosures of which are hereby incorporated herein by reference intheir entireties.

This application is related to commonly owned and assigned U.S. patentapplication Ser. No. 15/087,225, filed Mar. 31, 2016, entitled “BONDEDWAFERS AND SURFACE ACOUSTIC WAVE DEVICES USING SAME”; U.S. patentapplication Ser. No. 15/086,895, filed Mar. 31, 2016, now U.S. Pat. No.10,084,427, entitled “SURFACE ACOUSTIC WAVE DEVICE HAVING APIEZOELECTRIC LAYER ON A QUARTZ SUBSTRATE AND METHODS OF MANUFACTURINGTHEREOF”; and U.S. patent application Ser. No. 15/086,936, filed Mar.31, 2016, now U.S. Pat. No. 10,128,814, entitled “GUIDED SURFACEACOUSTIC WAVE DEVICE PROVIDING SPURIOUS MODE REJECTION,” which arehereby incorporated herein by reference in their entireties.

FIELD OF THE DISCLOSURE

The subject matter of the present disclosure relates to compositestructures having a resistance to the creation of a parasiticconductance between a piezoelectric layer and a silicon supportsubstrate and to Surface Acoustic Wave (SAW) filters implemented usingthese structures.

BACKGROUND

Surface Acoustic Wave (SAW) filters are used in many applications suchas Radio Frequency (RF) filters. For example, SAW filters are commonlyused in Second Generation (2G), Third Generation (3G), or FourthGeneration (4G) wireless transceiver front ends, duplexers, and receivefilters. The widespread use of SAW filters is due, at least in part, tothe fact that SAW filters exhibit low insertion loss with goodrejection, can achieve broad bandwidths, and are a small fraction of thesize of traditional cavity and ceramic filters. Usually, SAW filters useresonators at the surface of a piezoelectric crystal. The resonators maybe coupled electrically to form a so-called impedance element filter orladder filter. They may also be coupled acoustically by insertingseveral transducers between two reflectors, in which case, they form aCoupled Resonator Filter (CRF), also sometimes called a Double Mode SAWfilter (DMS). Hybrid architectures that cascade CRF stage and ladderstages may be used. The performance of the filter is depending on theindividual resonators characteristics.

Several parameters are important for a SAW resonator. One importantparameter is the effective piezoelectric coupling factor (K²), whichdepends on the ratio between antiresonance and resonance frequency. SAWresonators with larger coupling factors have larger frequency shiftsbetween resonance and antiresonance and can be used to design wide-bandfilters. The coupling factor mostly depends on the chosen piezoelectricsubstrate. Larger K² make possible the design of filters with a largerfractional bandwidth. Another important parameter of a SAW resonator isthe resonator Quality Factor (Q), which influences the insertion lossesof a filter designed with the SAW resonator and the steepness of thefilter response. Q depends mostly on the acoustic and electric losses inthe SAW resonator.

Also, the resonance frequency of a SAW resonator is proportional to thevelocity of the SAW. When the temperature changes, the velocity of thewave changes, and the filter shifts in frequency. Additionally, due tothermal expansion, the component dimensions change, leading also to anadditional frequency shift. SAW filters need to be able to select afrequency band for a temperature range that is typically a range of 100°Celsius (C) or more. A large thermal sensitivity of the center frequencyof a SAW filter results in a filter response shifting in frequency andoverall in degraded performances inside a given temperature range. Thethermal sensitivity is measured by a coefficient, which is typicallyreferred to as the Thermal Coefficient of Frequency (TCF). Mostmaterials have a negative TCF, meaning that the frequency decreases whenthe temperature increases.

SAW filters using leaky surface waves have losses due to the radiationof acoustic energy into the bulk substrate. One approach to reduce theselosses is to use a piezoelectric film at the surface of a supportsubstrate. For example, guided SAW devices have a layered substratewhere a piezoelectric layer is bonded or deposited on (e.g., directlyon) the surface of a support, or carrier, substrate. If the acousticvelocity of the support substrate is larger than the acoustic velocityin the piezoelectric film, the acoustic wave is guided inside the filmand the losses into the bulk are suppressed. This approach is beneficialonly if the piezoelectric film is thin enough. If a thick film is used,several spurious modes, due to higher order modes in the film, exist.Relatively thick films (10 wavelengths or so) may be used to improve thetemperature sensitivity but do not provide a significant reduction ofthe losses.

An improvement on this approach, which is described in the co-filed andcommonly-owned patent application U.S. Patent Application entitled“GUIDED SURFACE ACOUSTIC WAVE DEVICE PROVIDING SPURIOUS MODE REJECTION”and which discloses a bonded wafer comprising a piezoelectric layer overa non-semiconductor substrate, is to use piezoelectric thicknessesthinner than one or two wavelengths, which provides suppression of thebulk radiation losses with a limited or no spurious generation. It wasdiscovered that using this technique raised new challenges, however,when used with a semiconductor substrate: if the support substrate is asemiconductor like silicon, the quality factor is limited by a parasiticconductance inside the substrate. This is illustrated in FIGS. 1A and1B, which are not drawn to scale.

FIG. 1A shows a cross-section view of a SAW device constructed on aconventional bonded wafer 10 having a piezoelectric layer 12 ofthickness T_(OLD) over a silicon substrate 14 having a top surface 16.An array of electrodes 18 (only some of which are shown), referred toherein in singularly as the electrode 18 and in plurality as electrodes18, form electrical connections to the top surface of the piezoelectriclayer 12. A parasitic capacitance C exists between electrodes 18 and thesilicon substrate 14. FIG. 1A shows a conventional bonded wafer having athick piezoelectric layer 12, e.g., T_(OLD) is typically more than 10˜15times lambda (λ), which is the wavelength of the center operatingfrequency of the SAW device and is twice the period of the electrodes,where the “period” is the center-to-center distance between two adjacentelectrodes. Due to the bulk resistance of the silicon substrate 14, aninherent resistance R exists within the top surface 16 between parasiticcapacitors C. Due to the thickness of the piezoelectric layer 12, thevalue of C is small and therefore the effect of R on the performance ofthe device is negligible.

FIG. 1B shows a cross-section view of a SAW device built on a bondedwafer 20 having a very thin piezoelectric layer 12 having a thicknessT_(NEW), located above the silicon substrate 14. Compared to theconventional bonded wafer 10, the bonded wafer 20 has a larger parasiticcapacitance, C′, due to the relative thinness of the piezoelectriclayer. It was also discovered that, for a semiconductor substrate suchas silicon substrate 14, if T_(NEW) is less than ˜2λ, an inversion layerappears, shown in FIG. 1B as the line of electrons or charges located atthe top of the silicon substrate 14.

The presence of these additional charges creates a parasitic conductancethat reduces the resistance between the capacitors—i.e., the value R′ ofthe bonded wafer 20 is lower than the value of R within the conventionalbonded wafer 10—due to the parasitic conductance. The quality factor Qof a SAW filter is affected by R′: as the resistance R′ goes down, thefilter's quality factor drops.

FIGS. 2A and 2B are graphs illustrating the effect that a parasiticchannel has on admittance/conductance and Q, respectively, for thebonded wafer 20. In FIGS. 2A and 2B, the solid line represents theperformance of the device when the parasitic channel is absent, whilethe dotted line represents the performance of a device when a parasiticchannel is present. When the thickness of the piezoelectric layer isthinner, the influence of the transducer on the silicon substratebecomes larger and the reduction of the quality factor becomessignificant. FIGS. 2A and 2B illustrate the effects of a parasiticchannel when the piezoelectric layer 12 has a thickness T=0.5λ. In FIG.2A, it can be seen that the presence of the parasitic channel increasesthe conductance at antiresonance. In FIG. 2B, it can be seen that thepresence of the parasitic channel reduces the quality factor Qdrastically.

FIG. 2C is a graph illustrating how the thickness T of the piezoelectriclayer 12 affects the value of Q of a SAW resonator. The X-axis showsthickness T of the piezoelectric layer 12 in lambda. The Y-axis showsthe ratio of Q_(PAR) to Q_(NO-PAR) in %, where Q_(PAR) is the Q when theparasitic conductance is present and Q_(NO-PAR) is the Q when theparasitic conductance is not present. If the thickness T of thepiezoelectric layer 12 is more than 2×λ, Q is essentially unaffected. Ascan be seen in FIG. 2C, however, if T is less than 2×λ, Q becomesprogressively degraded as T is reduced, due to the presence of theparasitic channel. FIG. 2C shows that, without a parasitic channelpresent, the value of Q would have remained constant regardless of thethickness of the piezoelectric layer 12.

Thus, the presence of the parasitic conductance causes the appearance ofhigh conductivity paths that reduce the Q of the SAW resonators, whichdegrades the filter's performance. For SAW devices on bonded wafer 20,the piezoelectric layer 12 must have a thickness of at least 2×λ toavoid the creation of the parasitic conductance and the degradation of Qthat is caused by the presence of the parasitic channel. Because thepiezoelectric layer 12 of a bonded wafer 20 used for SAW filters must beat least 2λ thick, it is not possible to further reduce the thickness ofthe piezoelectric layer 12 in an effort to suppress the higher ordermodes in the piezoelectric film and to reduce the loss and thus enhancedevice performance.

Therefore, there is a need for a bonded wafer that resists the creationof a parasitic conductance at the top surface of the bulk siliconsubstrate during operation of the SAW filter so that a thinnerpiezoelectric layer may be used without degrading the performance of theSAW filter. One solution is to use a bonded wafer with low carrierlifetime in silicon.

SUMMARY

The present disclosure relates to methods of fabrication of a bondedwafer with low carrier lifetime in silicon and SAW devices implementedusing these structures.

According to one embodiment of the subject matter disclosed herein, amethod of fabricating a bonded wafer with low carrier lifetime insilicon comprises providing a silicon substrate having opposing top andbottom surfaces, modifying a top portion of the silicon substrate toreduce carrier lifetime in the top portion relative to the carrierlifetime in portions of the silicon substrate other than the topportion, bonding a piezoelectric layer having opposing top and bottomsurfaces separated by a distance T over the top surface of the siliconsubstrate, and providing a pair of electrodes having fingers that areinter-digitally dispersed on a top surface of the piezoelectric layer ina pattern having a center-to-center distance D between adjacent fingersof the same electrode, the electrodes comprising a portion of a SurfaceAcoustic Wave (SAW) device. The modified top portion of the siliconsubstrate prevents the creation of a parasitic conductance within thetop portion of the silicon substrate during operation of the SAW device.The modifying and bonding steps may be performed in any order, i.e., thetop portion of the silicon substrate may be modified before thepiezoelectric layer is bonded over it or after the piezoelectric layeris bonded over it (e.g., modification of the top portion of the siliconsubstrate may be via implantation through the piezoelectric layer).

In one embodiment, the thickness of the modified portion is at least 10nanometers. In another embodiment, the thickness of the modified portionis at least 50 nanometers. In yet another embodiment, the thickness ofthe modified portion is at least 200 nanometers.

In one embodiment, providing the piezoelectric layer comprises providinga layer comprising quartz, lithium niobate (LiNbO₃), or lithiumtantalate (LiTaO₃).

In one embodiment, the silicon substrate is monocrystalline and wheremodifying the top portion of the silicon substrate comprises modifyingthe top portion to be non-monocrystalline. In one embodiment, the topportion is modified to have a defect density in a range from 1e17/cm³ to1e22/cm³. In one embodiment, modifying the top portion of the siliconsubstrate comprises modification by damage implantation. In oneembodiment, modifying the top portion of the silicon substrate comprisesmodification by growth or deposition of polycrystalline silicon,nanocrystalline silicon, and/or amorphous silicon.

In one embodiment, modifying the top portion of the silicon substratecomprises modification by inclusion of deep trap impurities. In oneembodiment, the top portion is modified to have an impurity density in arange from 1e15/cm³ to 1e18/cm³.

In one embodiment, the modified top portion has a carrier lifetime ofless than 100 nanoseconds.

In one embodiment, thickness of the piezoelectric layer T is less than2*D. In one embodiment, T is greater than (0.10*D) for bonded waferswithout an insulation layer, and T is greater than (0.05*D) for bondedwafers that include an insulation layer. In one embodiment, T is lessthan (1.76−2.52e−4*(V_(SUB)+4210−V_(PIEZO)))*D, where V_(SUB) is thevelocity of the slowest acoustic wave in the propagation direction inthe substrate and V_(PIEZO) is the SAW velocity in the piezoelectriclayer.

In one embodiment, the method further comprises providing an insulationlayer between the silicon substrate and the piezoelectric layer. Themodifying and providing an insulation layer steps may be performed inany order. In one embodiment, providing the insulation layer between thesilicon substrate and the piezoelectric layer comprises growing ordepositing the insulation layer on the top surface of the siliconsubstrate prior to bonding the piezoelectric layer to the top surface ofthe insulation layer. In one embodiment, providing the insulation layerbetween the silicon substrate and the piezoelectric layer comprisesgrowing or depositing the insulation layer on the bottom surface of thepiezoelectric layer before bonding the insulation layer to the topsurface of the silicon substrate. In one embodiment, providing theinsulation layer comprises providing a layer of silicon oxide (SiO_(x)).In embodiments with an insulation layer T may be less than(1.76−2.52e−4*(V_(SUB)+4210−V_(PIEZO))−(0.50*T_(I)))*D, where V_(SUB) isthe velocity of the slowest acoustic wave in the propagation directionin the substrate, V_(PIEZO) is the SAW velocity in the piezoelectriclayer, and T_(I), is the thickness of the insulation layer. In oneembodiment, T_(I)<(0.1*D).

In one embodiment, the method further comprises embedding or coveringthe pair of electrodes by at least one dielectric, insulation, orpassivation layer.

In one embodiment, the method further comprises doping at least oneinsulation, dielectric, or passivation layer with Fluorine or Boroncompounds.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description in association with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure, andtogether with the description serve to explain the principles of thedisclosure.

FIG. 1A shows a cross-section view of a SAW device constructed on aconventional bonded wafer 10 having a thick piezoelectric layer over asilicon substrate;

FIG. 1B shows a cross-section view of a SAW device built on a bondedwafer 20 having a very thin piezoelectric layer above the siliconsubstrate;

FIGS. 2A and 2B are graphs illustrating the effect that a parasiticchannel has on admittance/conductance and Q, respectively, for a bondedwafer 20;

FIG. 2C is a graph illustrating how the thickness T of the piezoelectriclayer affects the value of Q of a SAW resonator;

FIG. 3 illustrates a cross-section view of an exemplary bonded waferwith low carrier lifetime in silicon according to an embodiment of thesubject matter described herein;

FIG. 4 is a graph comparing the performance of a SAW device made using abonded wafer 20 versus one made using an exemplary bonded wafer 22 thathas been treated via damage implantation;

FIG. 5 illustrates a cross-section view of an exemplary bonded waferwith low carrier lifetime in silicon according to another embodiment ofthe subject matter described herein;

FIG. 6 is an isometric view of a SAW device according to anotherembodiment of the subject matter described herein;

FIG. 7 is an isometric view of a SAW device according to anotherembodiment of the subject matter described herein;

FIGS. 8A and 8B are flow charts illustrating exemplary processes forfabricating a bonded wafer with low carrier lifetime according to anembodiment of the subject matter described herein;

FIGS. 9A and 9B are graphs illustrating the performance of a bondedwafer with different thicknesses of piezoelectric and insulation layersaccording to embodiments of the subject matter described herein; and

FIGS. 10A and 10B are graphs showing how proper selection ofpiezoelectric layer thickness can further improve the performance of theSAW device according to embodiments of the subject matter describedherein;

FIG. 11 is a flow chart illustrating an exemplary process forfabricating a bonded wafer with low carrier lifetime according toanother embodiment of the subject matter described herein;

FIG. 12 is a flow chart illustrating an exemplary process forfabricating a bonded wafer with low carrier lifetime according to yetanother embodiment of the subject matter described herein; and

FIG. 13 is a flow chart illustrating an exemplary process forfabricating a bonded wafer with low carrier lifetime according to stillanother embodiment of the subject matter described herein.

Those skilled in the art will recognize improvements and modificationsto the present disclosure. All such improvements and modifications areconsidered within the scope of the concepts disclosed herein.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region, orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer,region, or substrate is referred to as being “over” or extending “over”another element, it can be directly over or extend directly over theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly over” or extending“directly over” another element, there are no intervening elementspresent.

It will also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or there may be interveningelements present. In contrast, when an element is referred to as being“directly connected” or “directly coupled” to another element, there areno intervening elements present.

It will also be understood that although relative terms such as “above,”“below,” “top,” “middle,” “intermediate,” “bottom,” “upper,” “lower,”“horizontal,” “vertical,” “left,” “center,” “right,” and the like may beused herein to describe a relationship of one element, layer, or regionto another element, layer, or region as illustrated in the Figures,these elements should not be limited by these terms. It will beunderstood that these terms and those discussed above are intended toencompass different orientations of the device in addition to theorientation depicted in the Figures. For example, a first element couldbe termed an “upper” element and, similarly, a second element could betermed an “upper” element depending on the relative orientations ofthese elements, without departing from the scope of the presentdisclosure.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including” when used herein specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

FIG. 3 illustrates a cross-section view of an exemplary bonded wafer 22with low carrier lifetime in silicon according to an embodiment of thesubject matter described herein. In the embodiment illustrated in FIG.3, the exemplary bonded wafer 22 includes a silicon substrate 24 havingan opposing top surface 26 and bottom surface 28. The top of siliconsubstrate 24 has been modified or treated to reduce the carrier lifetimein a top portion 30 of the silicon substrate 24 (hereinafter referred tosimply as “the top portion 30” for brevity) relative to the carrierlifetime in portions of the silicon substrate 24 other than the topportion 30. It should be noted that the thickness of the top portion 30is not to scale: in one embodiment, the top portion 30 is about 300 nmthick, but this thickness is greatly exaggerated for the purposes ofillustration here. Thicknesses of 50 nm have also been shown to work.

A piezoelectric layer 32 having an opposing top surface 34 and bottomsurface 36 is bonded over the silicon substrate 24. The piezoelectriclayer 32 has a thickness, T. The relative thicknesses of the siliconsubstrate 24, the top portion 30, and the piezoelectric layer 32 arealso not to scale. In one embodiment, the piezoelectric layer 32comprises lithium tantalate (LiTaO₃), also referred to as “LT”. Othermaterials that may be used for the piezoelectric layer 32 include, butare not limited to, quartz and lithium niobate (LiNbO₃), also referredto as “LN”. In some embodiments, the piezoelectric layer is formed of LTwith an orientation between Y and Y+60 degrees. In other embodiments,the piezoelectric layer is formed of LN with an orientation between Y−20degrees and Y+60 degrees.

Unlike the conventional bonded wafer 10 illustrated in FIGS. 1A and 1B,the exemplary bonded wafer 22 is resistant or immune to the creation ofthe parasitic conductance shown in FIG. 1B. Under the influence of anelectric field through or normal to the top surface of the piezoelectriclayer 32, which may be generated when a voltage is applied to electrodes38, the top portion 30 prevents the creation of a parasitic conductancewithin the top 26 of the silicon substrate 24. This means that SAWdevices that are built using the exemplary bonded wafer 22 can be madewith a piezoelectric layer 32 that is less than 2×λ thick with nodegradation of Q. Such devices can have a piezoelectric layer 32 that isas thin as 0.10λ. As will be described in more detail below, with theaddition of an insulation layer between the piezoelectric layer 32 andthe silicon substrate 24, the piezoelectric layer 32 can be as thin as0.05λ.

The top 26 of the silicon substrate 24 may be treated in severaldifferent ways to reduce carrier lifetime. In one embodiment, thesilicon substrate 24 is monocrystalline and the top portion 30 has beenmodified to be non-monocrystalline. In one embodiment, this is achievedby subjecting the top portion 30 to damage implantation, e.g., byimplanting silicon (Si), argon (Ar), nitrogen (N), oxygen (O), neon(Ne), beryllium (Be), carbon (C), or krypton (Kr) ions. Protonimplantation may be used as well. Implantation destroys or fractures theregular crystalline structure of the top portion 30. In one embodiment,damage implantation may be performed until the top portion 30 has adefect density sufficient to impair the ability of the top portion 30 tobehave like a semiconductor. In one embodiment, damage implantation maybe performed until the top portion 30 has a defect density in a rangefrom 1e17/cm³ to 1e22/cm³.

In another embodiment, the top portion 30 of the silicon substrate 24has been modified by the growth or deposition of polycrystallinesilicon, nanocrystalline silicon, and/or amorphous silicon. Unlikemonocrystalline silicon, which has no grain boundaries due to itsregular crystal structure, polycrystalline silicon has large grains andamorphous silicon has small grains. In one embodiment, thepolycrystalline silicon has a grain size of 5 micrometers or less. Thesegrain boundaries also impair the ability of the top portion 30 to behavelike a semiconductor. The breaks in the regular crystalline structurethat are caused by damage implantation and that are inherent inpolycrystalline and amorphous silicon are locations within the crystalwhich may trap free carriers, reducing the carrier lifetime. RapidThermal Annealing (RTA)-crystallized polysilicon is another suitablemodification or treatment. Likewise, the regular crystalline structuremay be made irregular by etching or other mechanical and/or chemicalprocess.

Another way to treat the top portion 30 of silicon substrate 24 in orderto reduce carrier lifetime is by inclusion of deep trap impurities. Inthis technique, impurities such as gold (Au), vanadium (V), cobalt (Co),zinc (Zn), and copper (Cu) ions are interspersed among the silicon atomsvia implantation, diffusion, or other mechanism. The impurities alsotrap free carriers, reducing the carrier lifetime. In one embodiment,the top portion 30 may be subjected to deep trap impurities until thetop portion 30 has an impurity density sufficient to impair the abilityof the top portion 30 to behave like a semiconductor. In one embodiment,the top portion 30 has been modified to have an impurity density in arange from 1e15/cm³ to 1e18/cm³.

Neutron irradiation is yet another way to treat the top portion 30 ofsilicon substrate 24 in order to reduce carrier lifetime. Othertechniques that reduce the carrier lifetime of the top portion 30relative to other portions of the silicon substrate 24 are alsocontemplated, including combinations of any of the above treatments. Forexample, polycrystalline silicon may be combined with oxygen doping toproduce oxygen-doped polycrystalline silicon. Other combinations arecontemplated. In one embodiment, the top portion 30 has a carrierlifetime of less than 100 nanoseconds. With such a short carrierlifetime, the top portion 30 resists or is immune to the creation of theinversion layer to which the conventional bonded wafer 10 issusceptible.

In one embodiment, the wafer includes a dielectric overlay, insulation,or passivation layer, which may help reduce the temperature sensitivityof the SAW device. In one embodiment, the overlay can include siliconoxide which can be doped with for example Fluorine or Boron compounds toreduce further the temperature sensitivity. If silicon oxide is presentbetween the substrate and piezoelectric film it can be doped as well.

FIG. 4 is a graph comparing the performance of a SAW device made using abonded wafer 20 without any treatments to reduce the carrier lifetimeversus one made using an exemplary bonded wafer 22 that has been treatedvia damage implantation. FIG. 4 shows the value of Q over a range offrequencies from 880 MHz to 1080 MHz. The solid line represents thevalue of Q for a bonded wafer 20 without implantation and the patternedline represents the value of Q for an exemplary bonded wafer 22 withdamage implantation. It can be seen that the values of Q for theexemplary bonded wafer 22 are generally much higher than for the bondedwafer 20.

In one embodiment, bonded wafer 22 may include additional layers betweenthe piezoelectric layer 32 and the silicon substrate 24. One example ofthis is shown in FIG. 5.

FIG. 5 illustrates a cross-section view of an exemplary bonded waferwith low carrier lifetime in silicon according to another embodiment ofthe subject matter described herein. In the embodiment illustrated inFIG. 5, an exemplary bonded wafer 40 includes the silicon substrate 24having the opposing top surface 26 and bottom surface 28. The top 26 ofthe silicon substrate 24 has been modified or treated to reduce thecarrier lifetime in the top portion 30 of the silicon substrate 24relative to the carrier lifetime in portions of the silicon substrate 24other than the top portion 30. The exemplary bonded wafer 40 also hasthe piezoelectric layer 32 having the opposing top surface 34 and bottomsurface 36 and a thickness, T.

In the embodiment illustrated in FIG. 5, the exemplary bonded wafer 40includes an insulation layer 42 between the piezoelectric layer 32 andthe silicon substrate 24. In one embodiment, the insulation layer 42 iscomprised of silicon oxide (SiO_(x)), where x is normally close to 2(i.e., silicon dioxide, or SiO₂) but can vary, or other insulatingmaterial. Additionally, this silicon oxide layer can be doped with, forexample, fluorine or boron compounds to reduce temperature sensitivityof the device. Here, also, the relative thicknesses of the siliconsubstrate 24, its top portion 30 (also referred to herein as the lowcarrier lifetime portion 30), the insulation layer 42, and thepiezoelectric layer 32 are also not to scale.

FIG. 6 is an isometric view of a SAW device according to anotherembodiment of the subject matter described herein. In the embodimentillustrated in FIG. 6, a SAW resonator 44 includes the silicon substrate24, the top of which has been treated or modified to reduce the carrierlifetime in the top portion 30 of the silicon substrate 24 relative tothe carrier lifetime in portions of the silicon substrate 24 other thanthe top portion 30, which prevents the creation of a parasiticconductance at the top of the silicon substrate 24 during operation ofthe SAW device. Bonded above the silicon substrate 24 is thepiezoelectric layer 32 of thickness T and having opposing top and bottomsurfaces. Various types of SAW elements may be formed on the top surfaceof the piezoelectric layer 32. The piezoelectric layer 32 may be anypiezoelectric material such as, for example, quartz, lithium niobate(LiNbO₃), or lithium tantalate (LiTaO₃). In the embodiment illustratedin FIG. 6, the SAW resonator 44 includes a first pair of electrodes 38-1and 38-2 forming an Interdigitated Transducer (IDT). Each electrode 38-1and 38-2 includes multiple fingers having a center-to-center distance D,where D=λ, the wavelength of the center operating frequency of the SAWresonator 44. Because the electrodes are interdigitated, thecenter-to-center distance D for each electrode is twice distance betweenadjacent electrodes, i.e., D is twice the period. The IDTs generallyhave a much larger number of fingers than depicted; the number offingers has been significantly reduced in the drawing figures in aneffort to more clearly depict the overall concepts employed in availableSAW architectures as well as the concepts provided by the presentdisclosure. Additional fingers 46 on each side of the IDT electrodes38-1 and 38-2 comprise reflectors. For simplicity, only a very simpledevice is represented in FIG. 6 and other figures, but any kind of SAWdevice such as, for example, a resonator, a coupled resonator filter, aladder filter, an impedance element filter or a duplexer can used.

FIG. 6 illustrates the point that due to the presence of the low carrierlifetime portion 30 at the top of the silicon substrate 24, thepiezoelectric layer 32 can be thin (e.g., T<(2×λ)) without degradationof the Q of the SAW resonator 44, something that is not possible withbonded wafers 20. In the embodiment illustrated in FIG. 6, for example,T is approximately equal to λ, but using the exemplary bonded wafer 22,T can be as low as 0.10×λ without affecting Q. In one embodiment,T<(2×λ). In one embodiment, T<(1.76−2.52e−4*(V_(SUB)+4210−V_(PIEZO)))*D.Typical values for V_(SUB) range from 4210˜6984, depending on thesubstrate material.

It should be noted that the measurements listed above in terms of λ mayalso be made in terms of D. For example, in one embodiment, thethickness of T of the piezoelectric layer 32 may be less than 2*D. Inanother embodiment, T is greater than 0.10*D. From an operationalstandpoint, T may be defined in terms of λ and vice-versa; from astructural standpoint, T may be defined in terms of D and vice-versa.For the figures below, T is defined in terms of D for convenience butcould also be defined in terms of λ instead.

FIG. 7 is an isometric view of a SAW resonator 45 according to anotherembodiment of the subject matter described herein. In the embodimentillustrated in FIG. 7, the SAW resonator 45 includes the siliconsubstrate 24, the top portion of which has been treated or modified tocreate a low carrier lifetime portion 30. Above the silicon substrate 24is the insulation layer 42 having a thickness T_(I), which is bonded tothe piezoelectric layer 32 having a thickness T_(P). The SAW resonator45 illustrated in FIG. 7 is substantially identical to the SAW resonator44 illustrated in FIG. 6, except that the SAW resonator 45 is built on abonded wafer that includes an insulation layer 42.

FIG. 7 illustrates the point that, due to the presence of both the lowcarrier lifetime portion 30 at the top of the silicon substrate 24 andthe insulation layer 42, the piezoelectric layer 32 can be very thin,e.g., T_(P)>(0.05*D), without affecting Q.

FIG. 8A is a flow chart illustrating an exemplary process forfabricating a bonded wafer with low carrier lifetime according to anembodiment of the subject matter described herein. In the embodimentillustrated in FIG. 8A, the process includes: providing a siliconsubstrate having opposing top and bottom surfaces (step 100); modifyingthe silicon in a top portion of the silicon substrate to reduce thecarrier lifetime in the top portion relative to the carrier lifetime inportions of the silicon substrate other than the top portion (step 102);providing a piezoelectric layer over the silicon substrate havingopposing top and bottom surfaces separated by a distance T (step 104);and providing a pair of electrodes having fingers that areinter-digitally dispersed on the top surface of the piezoelectric layerin a pattern having a center-to-center distance D between adjacentfingers of the same electrode, where T<2*D (step 106).

In one embodiment, the method of fabricating a bonded wafer with lowcarrier lifetime includes bonding the piezoelectric layer to the siliconsubstrate. The piezoelectric layer may be formed by bonding apiezoelectric wafer on the substrate and by reducing its thickness bymechanical grinding/polishing.

FIG. 8B is a flow chart illustrating in more detail step 104 of FIG. 8Aaccording to an embodiment of the subject matter described herein. Inthe embodiment illustrated in FIG. 8B, providing a piezoelectric layerover the silicon substrate starts with providing a piezoelectricmaterial, such as a wafer or film, that has not yet been bonded to thesubstrate (step 108); forming a fragile layer inside the piezoelectricmaterial at a controlled depth from the top surface of the piezoelectricmaterial by implantation (step 110); bonding the bottom surface of thepiezoelectric material to the top surface of the substrate (step 112);splitting the piezoelectric material by breaking it at the fragile layerand removing the piezoelectric material above the fragile layer (step114); and polishing the top surface of the piezoelectric material thatis still bonded to the substrate (step 116), e.g., polishing the surfaceof that was previously part of the internal fragile layer. In oneembodiment, thermal stress may be used to split the piezoelectricmaterial at the fragile layer.

In one embodiment, modifying the top portion of the silicon substratecomprises modifying the top portion of the silicon substrate to benon-monocrystalline. In one embodiment, modifying the top portion of thesilicon substrate to be non-monocrystalline comprises modification bydamage implantation. In one embodiment, modification by damageimplantation comprises implantation of silicon ions, argon ions,nitrogen ions, oxygen ions, neon ions, beryllium ions, carbon ions,krypton ions, and/or protons.

In one embodiment, modifying the top portion of the silicon substrate tobe non-monocrystalline comprises modification by the growth ordeposition of polycrystalline silicon, nanocrystalline silicon, and/oramorphous silicon.

In one embodiment, modifying the top portion of the silicon comprisesmodifying the top portion of the silicon substrate to include deep trapimpurities. In one embodiment, the deep trap impurities comprise goldions, vanadium ions, cobalt ions, zinc ions, and/or copper ions.

In one embodiment, modifying the top portion of the silicon substrateincludes modifying the top portion of the silicon substrate to have alow carrier lifetime relative to the carrier lifetime within portions ofthe silicon substrate other than the top portion.

In one embodiment, the modification of the top portion prevents thecreation of a parasitic conductance within the top of the siliconsubstrate during operation of a surface acoustic wave device built usingthe exemplary bonded wafer.

In one embodiment, the method of fabrication includes providing aninsulation layer between the silicon substrate and the piezoelectriclayer. In these embodiments, the method includes bonding thepiezoelectric layer to the insulation layer.

FIGS. 9A and 9B are graphs illustrating the performance of the exemplarybonded wafer 40 with different thicknesses of the piezoelectric layer 32and the insulation layer 42 according to embodiments of the subjectmatter described herein. The thickness T of the piezoelectric layer 32is shown on the X axis and the characteristic being simulated isdisplayed on the Y axis. Each curve represents the performance of abonded wafer with a different thickness of the insulation layer 42 interms of λ.

In FIG. 9A, the value of K² is shown as a percentage on the Y axis. FIG.9A shows that K² values as high as 8% can be achieved with no insulationlayer (SiO₂=0.00λ) even when T is 0.10λ. With the addition of a smallinsulation layer (SiO₂>0.02λ), comparable K² values can be achieved evenwhen T is 0.05λ. In the graph illustrated in FIG. 9A, T=0.15λ is anoptimal thickness of the piezoelectric layer 32.

In FIG. 9B, the value of resonance frequency f is shown in megahertz(MHz) on the Y axis. FIG. 9B shows that a SiO₂ thickness of 0.08λ has arelatively flat response with variation of thickness T of thepiezoelectric layer 32 around the target thickness T=0.15λ. In otherwords, a process variation of T between 0.10λ and 0.20λ will cause onlya slight variation of the resonance frequency of ˜950 MHz.

FIGS. 10A and 10B are graphs showing how proper selection ofpiezoelectric layer thickness can further improve the performance of theSAW device according to embodiments of the subject matter describedherein.

FIGS. 10A and 10B show the simulated admittance and conductance of aguided SAW resonator built using the exemplary bonded wafer 22, forexample. Conductance rapidly increases at the cutoff frequency because,above the cutoff frequency, the bulk acoustic wave is not containedwithin the piezoelectric layer 32 but instead disperses into the siliconsubstrate 24. The cutoff frequency is a function of the velocity in thesupport substrate (V_(SUB)), which is itself a function of the supportsubstrate material: higher velocity means a higher cutoff frequency. InFIGS. 10A and 10B, the cutoff frequency is about 1.18 GHz for a siliconsubstrate.

The frequency of the spurious modes, however, is influenced by thethickness T of the piezoelectric layer 32. FIG. 10A shows that, forT=0.7λ, spurious modes appear between 1.1 GHz and 1.2 GHz. FIG. 10Bshows that if T is reduced to 0.5λ the spurious modes appear between 1.2GHz and 1.3 GHz, i.e., at a frequency higher than the cutoff frequency,which causes those modes to be suppressed. Because the cutoff frequencyis not dependent upon T, T may be adjusted to frequency-shift thespurious modes into a frequency above the cutoff frequency, where thespurious modes will be suppressed. Thus, by thoughtful selection of T,the overall performance of a SAW resonator may be improved. Forsuppression of spurious modes, it has been determined by simulation thatT should be less than about (1.76−2.52e−4*(V_(SUB)+4210−V_(PIEZO)))*D.For bonded wafers with an insulation layer having a thickness T_(I),thickness of the piezoelectric layer T should be less than about(1.76−2.52e−4*(V_(SUB)+4210−V_(PIEZO))−0.50*T_(I))*D. In one embodiment,T_(I), is less than (0.1*D). Since different substrate materials havedifferent values for V_(SUB), the thickness of the piezoelectric layer32 needed to suppress the spurious modes would differ from substratematerial to substrate material. For example: for silicon, T should beless than about 0.60λ; for sapphire, T should be less than about 0.25λwhen 42LT is used as a piezoelectric layer.

The equations above are for general purpose including lithium tantalate,lithium niobate, quartz, and other piezoelectric materials as apiezoelectric layer. However, for rotated Y-cut lithium tantalate (LT)layer, for example, the value of V_(PIEZO) varies depending upon the cutangle θ. The following equations should be used to determine a maximumthickness of the piezoelectric layer for suppression of spurious modesbased on the cut angle of the rotated Y-cut LT layer:T<(1.76−2.52×10⁻⁴×(V_(SUB)+4210−(−2.435×10⁻⁹θ⁶+1.103×10⁻⁶θ⁵−1.719×10⁻⁴θ⁴+1.145×10⁻²θ³−4.229×10⁻¹θ²+9.765θ+4.103×10³)))×lambdafor bonded wafers without an insulation layer, andT<(1.76−2.52×10⁻⁴×(V_(SUB)+4210−(−2.435×10⁻⁹θ⁶+1.103×10⁻⁶θ⁵−1.719×10⁻⁴θ⁴+1.145×10⁻²θ³−4.229×10⁻¹θ²+9.765θ+4.103×10³))−0.50×T_(I))×lambdafor bonded wafers with an insulation layer having a thickness T_(I).

FIG. 11 is a flow chart illustrating an exemplary process forfabricating a bonded wafer with low carrier lifetime according toanother embodiment of the subject matter described herein. In theembodiment illustrated in FIG. 11, the process includes: providing asilicon substrate having opposing top and bottom surfaces (step 200);providing, over the top surface of the silicon substrate, apiezoelectric layer having opposing top and bottom surfaces separated bya distance T (step 202); thinning and/or polishing the piezoelectriclayer (step 204); and performing damage implantation or deep trap ionimplantation of the top surface of the silicon substrate through thepiezoelectric layer (step 206). FIG. 11 illustrates the point that thedamage implantation or deep trap ion implantation step can be performedafter the piezoelectric layer has been provided onto the top surface ofthe silicon substrate. In one embodiment, providing a piezoelectriclayer over the top surface of the silicon substrate may comprise bondingthe piezoelectric layer to the top surface of the silicon substrate.

FIG. 12 is a flow chart illustrating an exemplary process forfabricating a bonded wafer with low carrier lifetime according to yetanother embodiment of the subject matter described herein. In theembodiment illustrated in FIG. 12, the process includes: providing asilicon substrate having opposing top and bottom surfaces (step 300);providing an insulation layer over the top surface of the siliconsubstrate (step 302); providing, over the top surface of the insulationlayer, a piezoelectric layer having opposing top and bottom surfacesseparated by a distance T (step 304); thinning and/or polishing thepiezoelectric layer (step 306); and performing damage implantation ordeep trap ion implantation of the top surface of the silicon substratethrough both the piezoelectric layer and the insulation layer (step308). FIG. 12 illustrates the point that the damage implantation or deeptrap ion implantation step can be performed after both an insulatinglayer and the piezoelectric layer has been provided onto the top surfaceof the silicon substrate. In one embodiment, providing the insulationlayer over the top of the silicon substrate may comprise growing asilicon dioxide (or other oxide layer) on the top surface of the siliconsubstrate. It may also comprise bonding an insulating material to thetop surface of the silicon substrate. In one embodiment, providing apiezoelectric layer over the top surface of the insulation layer maycomprise bonding the piezoelectric layer to the top surface of theinsulation layer.

FIG. 13 is a flow chart illustrating an exemplary process forfabricating a bonded wafer with low carrier lifetime according to stillanother embodiment of the subject matter described herein. In theembodiment illustrated in FIG. 13, the process includes: providing asilicon substrate having opposing top and bottom surfaces (step 400);providing an insulation layer over the top of the silicon substrate(step 402); performing damage implantation or deep trap ion implantationof the top surface of the silicon substrate through the insulation layer(step 404); providing, over the top surface of the insulation layer, apiezoelectric layer having opposing top and bottom surfaces separated bya distance T (step 406); and thinning and/or polishing the piezoelectriclayer (step 408). FIG. 13 illustrates the point that the damageimplantation or deep trap ion implantation step can be performed afteran insulating layer has been provided onto the top surface of thesilicon substrate but before the piezoelectric layer is provided overthe top surface of the insulation layer. In one embodiment, providingthe insulation layer over the top of the silicon substrate may comprisegrowing a silicon dioxide (or other oxide layer) on the top surface ofthe silicon substrate. It may also comprise bonding an insulatingmaterial to the top surface of the silicon substrate. In one embodiment,providing a piezoelectric layer over the top surface of the insulationlayer may comprise bonding the piezoelectric layer to the top surface ofthe insulation layer.

It will be understood that the principles described above with respectto any particular SAW device, such as a resonator, also apply to othertypes of devices, including, but not limited to, ladder filters,impedance element filters, coupled resonator filters, or any combinationof the above, as well as to duplexers and filters included insideduplexers.

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

What is claimed is:
 1. A method of fabricating a bonded wafer with lowcarrier lifetime in silicon, the method comprising: providing a siliconsubstrate having opposing top and bottom surfaces; modifying a topportion of the silicon substrate to impair an ability of the top portionto behave like a semiconductor by forming locations in the top portionwhich trap free carriers; providing a piezoelectric layer over the topsurface of the silicon substrate, the piezoelectric layer havingopposing top and bottom surfaces separated by a distance T; andproviding a pair of electrodes having fingers that are inter-digitallydispersed on the top surface of the piezoelectric layer in a patternhaving a center-to-center distance D between adjacent fingers of thesame electrode, the electrodes comprising a portion of a SurfaceAcoustic Wave (SAW) device, the modified top portion of the siliconsubstrate preventing creation of a parasitic conductance within the topportion of the silicon substrate during operation of the SAW device,wherein modifying the top portion of the silicon substrate comprisesproviding metal ions in the top portion of the silicon substrate thatcause deep trap impurities to be included in the top portion of thesilicon substrate.
 2. The method of claim 1 wherein a thickness of themodified top portion is at least 10 nanometers.
 3. The method of claim 1wherein a thickness of the modified top portion is at least 50nanometers.
 4. The method of claim 1 wherein a thickness of the modifiedtop portion is at least 200 nanometers.
 5. The method of claim 1 whereinproviding the piezoelectric layer comprises providing a layer comprisingat least one of quartz, lithium niobate (LiNbO₃), or lithium tantalate(LiTaO₃).
 6. The method of claim 1 wherein T<(2*D).
 7. The method ofclaim 1 wherein T>(0.10*D).
 8. The method of claim 1 wherein:T<(1.76−2.52e−4*(V _(SUB)+4210−V _(PIEZO)))*D; V_(SUB) is a velocity ofa slowest acoustic wave in a propagation direction in the siliconsubstrate; and V_(PIEZO) is a SAW velocity in the piezoelectric layer.9. The method of claim 1 further comprising providing an insulationlayer between the silicon substrate and the piezoelectric layer, whereinproviding the metal ions in the top portion of the silicon substratecomprises one of: implanting the metal ions through the insulation layerand into the top portion of the silicon substrate; implanting the metalions through the piezoelectric layer and into the top portion of thesilicon substrate; or implanting the metal ions through thepiezoelectric layer and the insulation layer and into the top portion ofthe silicon substrate.
 10. A method of fabricating a bonded wafer withlow carrier lifetime in silicon, the method comprising: providing asilicon substrate having opposing top and bottom surfaces; providing aninsulation layer over the top surface of the silicon substrate;modifying a top portion of the silicon substrate to impair an ability ofthe top portion to behave like a semiconductor by forming locations inthe top portion which trap free carriers; providing a piezoelectriclayer over a top surface of the insulation layer, the piezoelectriclayer having opposing top and bottom surfaces separated by a distance T;and providing a pair of electrodes having fingers that areinter-digitally dispersed on the top surface of the piezoelectric layerin a pattern having a center-to-center distance D between adjacentfingers of the same electrode, the electrodes comprising a portion of aSurface Acoustic Wave (SAW) device, the modified top portion of thesilicon substrate preventing creation of a parasitic conductance withinthe top portion of the silicon substrate during operation of the SAWdevice, wherein modifying the top portion of the silicon substratecomprises implanting ions through at least the insulation layer and intothe top portion of the silicon substrate.
 11. The method of claim 10wherein: the silicon substrate is monocrystalline; and implanting theions into the top portion of the silicon substrate causes the topportion to comprise a non-monocrystalline structure having the locationswhich trap free carriers.
 12. The method of claim 11 wherein the topportion is modified to have a defect density in a range from 1e17/cm³ to1e22/cm³.
 13. The method of claim 11 wherein modifying the top portionof the silicon substrate comprises implanting the ions through thepiezoelectric layer and the insulation layer and into the top portion ofthe silicon substrate.
 14. The method of claim 13 wherein the ions areimplanted across a thickness of the top portion of the siliconsubstrate.
 15. The method of claim 13 wherein implanting the ions intothe top portion of the silicon substrate causes a defect density in arange from 1e17/cm³ to 1e22/cm³.
 16. The method of claim 10 whereinimplanting the ions into the top portion of the silicon substratecomprises implanting metal ions into the top portion of the siliconsubstrate that cause deep trap impurities to be included in the topportion of the silicon substrate.
 17. The method of claim 16 wherein thetop portion is modified to have an impurity density in a range from1e15/cm³ to 1e18/cm³.
 18. The method of claim 10 wherein the modifiedtop portion has a carrier lifetime of less than 100 nanoseconds.
 19. Amethod of fabricating a bonded wafer with low carrier lifetime insilicon, the method comprising: providing a silicon substrate havingopposing top and bottom surfaces; modifying a top portion of the siliconsubstrate to reduce carrier lifetime across a thickness of the topportion relative to a carrier lifetime in portions of the siliconsubstrate other than the top portion; providing a piezoelectric layerover the top surface of the silicon substrate, the piezoelectric layerhaving opposing top and bottom surfaces separated by a distance T; andproviding a pair of electrodes having fingers that are inter-digitallydispersed on the top surface of the piezoelectric layer in a patternhaving a center-to-center distance D between adjacent fingers of thesame electrode, the electrodes comprising a portion of a SurfaceAcoustic Wave (SAW) device, the modified top portion of the siliconsubstrate preventing creation of a parasitic conductance within the topportion of the silicon substrate during operation of the SAW device,wherein modifying the top portion of the silicon substrate comprisesproviding metal ions in the top portion of the silicon substrate thatcause deep trap impurities to be included within the top portion of thesilicon substrate.
 20. The method of claim 19 further comprisingproviding an insulation layer between the silicon substrate and thepiezoelectric layer, wherein the modifying and providing the insulationlayer steps are performed in any order.
 21. The method of claim 20wherein providing the insulation layer comprises providing a layer ofsilicon oxide.
 22. The method of claim 21 further comprising doping thelayer of silicon oxide with Fluorine or Boron compounds to reducethermal sensitivity of the SAW device.
 23. The method of claim 20wherein a thickness of the insulation layer is greater than (0.02*D).24. The method of claim 23 wherein providing the insulation layercomprises providing a layer of silicon oxide.
 25. The method of claim 20wherein:T<(1.76−2.52e−4*(V _(SUB)+4210−V _(PIEZO))−(0.50*T _(I)))*D; V_(SUB) isa velocity of a slowest acoustic wave in a propagation direction in thesilicon substrate; V_(PIEZO) is a SAW velocity in the piezoelectriclayer; and T_(I) is a thickness of the insulation layer.
 26. The methodof claim 20 wherein a thickness of the insulation layer is less than(0.1*D).
 27. The method of claim 19 further comprising embedding orcovering the pair of electrodes by at least one dielectric, insulation,or passivation layer.
 28. The method of claim 27 further comprisingdoping the at least one dielectric, insulation, or passivation layerwith Fluorine or Boron compounds.
 29. The method of claim 28 whereindoping the at least one of the insulation layer, the dielectric layer,or the passivation layer with Fluorine or Boron compounds reducesthermal sensitivity of the SAW device.